In some implementations, III-N material based transistors, such as gallium nitride (GaN) based transistors may be used for high voltage and/or high frequency applications. For example, power management integrated circuits (PMIC) and radio frequency integrated circuits (RFIC) may be critical functional blocks in system on a chip (SoC) implementations. Such SoC implementations may be found in mobile computing platforms such as smartphones, tablets, laptops, netbooks, and the like. In such implementations, the PMIC and RFIC are important factors for power efficiency and form factor (and can be as or more important than logic and memory circuits).
Gallium nitride based devices may be advantageous in some examples because GaN has a wide band gap (˜3.4 eV) as compared to silicon (Si: ˜1.1 eV). The wide band gap may allow a GaN transistor to withstand a larger electric field (e.g., applied voltage, VDD) before suffering breakdown as compared to Si transistors of similar dimensions. Furthermore, GaN transistors may employ a 2D electron gas (e.g., 2D sheet charge) as its transport channel. For example, the 2D sheet charge may be formed at an abrupt hetero-interface formed by epitaxial deposition of a charge-inducing film with larger spontaneous and piezoelectric polarization such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN) or aluminum indium nitride (AlInN) on GaN. Very high charge densities of up to 2×1013 per cm2 may be formed by such a mechanism without impurity dopants, allowing high mobilities of, for example, greater than 1000 cm2/(Vs).
For power management and radio frequency (RF) amplification, transistors may require large widths (e.g., greater than 1 mm) to deliver large currents (e.g., greater than 1 A) and large power (e.g., >1 W). Furthermore, to take full advantage of the discussed properties of GaN, the GaN transistors are typically heterogeneously integrated onto a Si substrate such that the GaN transistors may be placed in close proximity to Si CMOS devices. Such placement may minimize interconnect losses, provide for a smaller overall footprint, and provide scaling advantages.
As transistor pitch is reduced, the maximum breakdown voltage that a transistor may withstand may reduce proportionately with the shrinking of the gate-to-drain separation. Using current techniques, to withstand a larger breakdown voltage, the transistor gate-to-drain distance must be extended and the associated area penalty must be accepted. Using such techniques may require a trade-off between breakdown voltage and transistor scaling.
As such, existing techniques do not provide for scaling transistors to smaller pitches or increasing breakdown voltage at current pitches. Such problems may become critical in PMIC or RFIC implementations, for large voltage handling (e.g., direct battery connect, input/output, universal serial bus), or the like.